Intelligent Computing & Codesign Lab

In his masters thesis defense on Jan 9th, 2013, Toan presented an approach called Runtime Binary Translation (RBT) that can dynamically make use of the CGRA accelerator existing in a CGRA-based reconfigurable computing system to speedup the execution of application intermediate representation (IR) on top of a just-in-time (JIT) compiler.  A simpler approach called Install-time Binary Translation (IBT) based on RBT is also proposed. Here is the abstract of the thesis. 😀

Nowadays, softwares are often distributed in form of some machine-independent intermediate representation (IR), because compared to machine-dependent native binary, the IR is more portable across a wide range of architectures, has better security, and contains richer semantic information. However, the problem of making use of the accelerator in a target machine to speedup the execution of the IR on top of a just-in-time compiler (JIT) is challenging, mainly because the discovery of compute-intensive kernels and the partitioning of the application to the kernel and sequential parts must be done based on the IR alone, without the access to the program source code as well as the kernel information in the IR.

In this work, we propose a Runtime Binary Translation (RBT) technique that can dynamically identify and translate kernels IR to Coarse-Grained Reconfigurable Array (CGRA) accelerator configuration, and offload the execution of the kernels onto the accelerator. Also, we simplify the RBT approach to make the Install-time Binary Translation (IBT) approach, which does the partitioning and the translation right at the install-time instead of at the runtime. Experimental results show that our RBT and IBT techniques can improve the runtime of the application IR by 1.44 times and 1.61 times, respectively, compare to the runtime on the JIT that does not support making use of the accelerator.

Runtime Binary Translation Virtual Machine Optimized Design

Congratulations, Toan!

Yesterday, January 9, Toan successfully defended his thesis on Runtime and Install-time Binary Translation for Reconfigurable Accelerators. Though there are some minor things he has to finish before he can get the approval signatures from the committee members, the thesis committee was in general agreement that he did a good job for a masters degree, based on his achievements during the graduate program and his thesis writing.

Now that he is seeking an industry career at the moment, the ICCL lab wishes him a good luck in his career and a good fortune too! 🙂

Important Notice

To students taking CSE211: Introduction to Programming Languages, in the 3rd term of 2012.

The required textbook for this course is changed to Concepts of Programming Languages by Robert W. Sebesta, 10th edition, Addison-Wesley. You can purchase the textbook at the campus bookstore or online.

Jongeun Lee, The Instructor

Seminar Schedule for September/October (Place is EB1 E204 unless noted otherwise.)

Cloud Random Access Network (C-RAN)

• Speaker: Dr. Saewoong Bahk, Seoul National University
• Date: September 19
• Title: Evolution of Wi-Fi on Cloud-RAN: Complementary Utilization of Unlicensed Spectrum

Flash Memory Technology

• Speaker: Dr. Taehoon Kim, Intel-Micron joint R&D team for memory devices
• Date: September 26
• Title: Challenges & Future Directions for Flash & Emerging Nonvolatile memories for 2D & 3D realization

Automotive

• Speaker: Dr. Seungyoung Ahn, KAIST
• Date: October 10
• Title: Future Green Transportation with Wireless Power Transfer Technology

Mobile Application Processor

• Speaker: Dr. Jeong-Ho Woo, Texas Instruments
• Date: October 23
• Title: Design Paradigm of Mobile Application Processor

Multiprocessor Architecture: Design and Implementation

• Speaker: Dr. Jongmyon Kim, University of Ulsan
• Date: October 24
• Title: Mobile Multimedia Supercomputer Design

Our paper titled “Software-Managed Automatic Data Sharing for Coarse-Grained Reconfigurable Coprocessors” is accepted as an oral presentation in the International Conference on Field Programming Technology (FPT) 2012, which will be held in Seoul, Dec 10~12.

Congratulations to those who participated in this work!

Yes, you read it correctly.  It’s a rare combination of AI (Artificial Intelligence) and HW (Hardware) design skills, that is in want.

There is a national and an international competition that is scheduled around October, on FPGA designs that can play the “Connect-6” game. The connect-6 game is a variation of “Five-in-a-Row” (or Omok as is called in Korea), and the trick is that you have to make a hardware in FPGA that can play the game in real-time. The timing constraint is 1 min, and you have to come up with the best solution within the min — otherwise you’ll forfeit your chance to make a move.

*Highlights of this competition

• First place winner of the national level will be given a very prestigious MKE-ministry award (지식경제부 장관상).
• National level winners will enter the international level.
• International level winners will be recognized with cash prizes during an international conference (FPT), and their design summary will be published in the conference proceedings.

More details can be found in the conference website.

Sounds interesting?  Contact the lab. Don’t worry if you don’t have any knowledge/experience with AI or HW design — not expected (but you should be at least a junior majoring in ECE).

Some dynamic elements are added to the front page, which now shows a slideshow instead of a random picture. The slideshow controls are also provided (previous, next, and pause/resume). The previous and next buttons are easy to spot, but where is the pause/resume button?

The answer is the page number.

As part of the 2012 International Conference on Field Programming Technology, there will be a design contest for the best/fastest Connect-6 game designs.

For more details see website: http://www.eecg.toronto.edu/~janders/FPT_2011_competition/ (it is for the previous year, but this year’s rules will be similar)

또 한 가지 중요한 정보는 이 국제 대회를 준비하기 위하여 국내 대회를 개최할 예정입니다. 국내에서 처음으로 개최되는 대회이고 아직 공식 발표된 것이 아니기 때문에 누구든지 지금부터라도 준비하면 괜찮은 결과를 얻을 수 있습니다. 또 처음 개최되는 대회라서 참여를 독려하기 위해 많은 상이 마련되어 있는 것으로 알고 있습니다. 관심 있는 학생은 문의바랍니다.

This time, HiPEAC tries a new publication model. Instead of first publishing your paper in a conference, they do a journal review process for all submitted papers, and those accepted papers will have a chance to get presented in a conference, in addition to the journal publication. Our paper on nested loop compilation for reconfigurable architectures, was accepted for this journal issue. Congrats to those involved in this work!

Special high performance computing seminar by NVIDIA Korea

Friday (2011.11.25) 11:00 (EB1 E204).

1. 11:00~11:45 : GPU based render farm and Cloud computing trend

Speaker: JuSeok Lee

Bio:

• Sir Sales manager at NVIDIA Korea professional solution group
• Director of CSE(Korea Computational science and technology Society)
• 2004.Oct ~2007.Feb : sales at Intel Korea CISD, handheld business unit
• Graduated from Yonsei University, Physics department

2. 11:45~12:30 : CUDA, Parallel Programming with GPU without Tears

Speaker: Hyungon Ryu

Bio:

• Solution Architect at NVIDIA Korea Professional Solution Group
• 2009. Jan. ~ work for NVIDIA Korea
• 2006. Mar. ~ Dept. of Mathematics. Yonsei Univ. (PhD. Candidate)