Internship position available

June 4th, 2015 Comments off

Internship Positions at ICCL, UNIST

The Embedded Computing Laboratory at UNIST is recruiting 
multiple undergraduate researchers in the broad area of 
brain-inspired computing as described below.


FPGA-based Deep Learning

Recent advances in deep learning are in large part due to the increased computing capability of off-the-shelf processors. To enable further advances in this direction, this project explores the use of “programmable hardware”, or FPGA (Field-Programmable Gate Array) technology, for the acceleration of deep neural networks such as convolutional neural networks. In a broader context, this research topic is about the application of hardware-software co-design principles to machine learning algorithms, which has many implications and is in active research nowadays.

This topic is best suited for students majoring in both CSE and EE (it doesn’t matter whichever is the 1st major). Prerequisites include Computer Organization, and exposure to hardware description languages is a strong plus. Knowledge of Machine Learning or Artificial Intelligence is a plus, but not required.

Stochastic Deep Neural Network

Creating a Deep Neural Network (DNN) processor has many appeals. A DNN processor can be much more efficient than CPU/GPU/FPGA-based implementations, thus enabling a host of interesting applications (e.g., real-time image recognition), and being a processor, it can be applied to many different neural network applications. Challenges however include how to make it scalable to large and small networks. One idea is to apply Stochastic Computing (SC). SC is a new way of representing numbers and performing arithmetic operations, and radically different from conventional digital computing and enables much more compact implementations of complex functions.

Best candidates for this topic should have strong math skills (especially in probability). Machine learning or hardware design is not a requirement.


Interested students should contact Prof. Lee.

Note: These research positions are related to Samsung Future Technology Project.

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Samsung Future Technology project

June 1st, 2015 Comments off




Sponsored by Samsung Future Technology Center,

we have launched a new, ambitious project on brain-inspired computing,

titled Reconfigurable Deep Neural Network Processor Based on Stochastic Computing.


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Old boys

May 30th, 2015 Comments off





Old boys visiting ICCL lab today.

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Matrix here

March 20th, 2015 Comments off

IEEE Spectrum introduces how neural circuitry implanted in our brain can do life-saving work. Though the article doesn’t give out much info about the kind of neural circuity implanted, it does mention microprocessor and battery. So it looks like a really low power microprocessor running some kind of algorithm similar to neural net. The article suggests that learning takes place offline, but is silent on how the parameter update can be done or how easy/unintrusive it is.

Either way it shows another very compelling application for embedded systems capable of machine learning tasks.

Bionic woman, but the striking similarity with Matrix is undeniable. (via IEEE)

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Sangyun Oh

March 1st, 2015 Comments off

Sangyun Oh

Sangyun Oh started his M.S. program in March, 2015. His research interests include (i) reconfigurable architecture and (ii) acceleration of deep neural networks for low-power systems.

He received a best paper award at KCS conference, 2017.

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Paper accepted to DAC 2015

February 17th, 2015 Comments off

Congratulations! Our paper “Optimizing Stream Program Performance on CGRA-based Systems,” authored by Hongsik Lee, Dong M. Nguyen, and Jongeun Lee (all currently at UNIST) is accepted to DAC (Design Automation Conference) this year. This work was in large part based on the work of Seongseok Seo, who graduated UNIST with a master’s degree one year ago. Seongseok’s primary work, which was presented at the last year’s CODES+ISSS conference, was about a light-weight yet highly effective hardware extension for mapping nested loops often found in DSP (Digital Signal Processing) applications. This work takes it to another level, developing application-level mapping strategies for stream applications with comparisons to GPU mapping results.

The DAC conference is frequently the highest ranked conference in the area of electronic design automation. It is also widely recognized as one of the most prestigious conferences in the electrical engineering and computer science discipline.

DAC 2015

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Paper presentations at the 22nd KCS

January 31st, 2015 Comments off


(Image from via google image)

The 22nd Korean Conference on Semiconductors (KCS) is one of the largest conferences held in Korea in the electronic engineering discipline. Last year KCS attracted about 1,300 attendees from academia and industry. KCS also boasts a strong technical program consisting of about 300~400 oral+poster presentations annually.

This year the ICCL lab has three oral paper presentations, on high-level synthesis presented by Atul Rahman, coarse-grained reconfigurable architecture by Hongsik Lee, and application mapping for GP-GPUs (General-Purpose Graphics Processing Units) by Dong M. Nguyen.

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Welcome dinner

September 4th, 2014 Comments off


Welcoming Atul!

Photo credit: Hyeon Uk took this photo.

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Atul Rahman

September 1st, 2014 Comments off

Atul Rahman

Atul Rahman is a graduate student, beginning his M.S. program in September, 2014. His research interests include high-level synthesis and approximate/stochastic computing.

He won the Samsung HumanTech Award in 2016, and is the first author of two papers presented in the Design, Automation and Test in Europe (DATE) Conference, in 2016 and 2017. In 2016 he joined Samsung Electronics, in Suwon, Korea.

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Paper accepted to CODES+ISSS 2014

June 30th, 2014 Comments off


Our paper, titled “Flattening-based Mapping of Imperfect Loop Nests for CGRAs” by Jongeun Lee, Seongseok Seo, Hongsik Lee, and Hyeon Uk Sim, is accepted to this year’s CODES+ISSS (International Conference on Hardware-Software Codesign and System Synthesis).

CODES+ISSS is is a premier conference for embedded systems and hardware software co-design research, and held as part of ESWEEK (Embedded Systems Week) event, which also includes CASES (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems) and EMSOFT (International Conference on Embedded Software), along with a host of workshops and symposia. Congratulations again to those who did the hard work!

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