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Paper accepted to CODES+ISSS 2014

June 30th, 2014


Our paper, titled “Flattening-based Mapping of Imperfect Loop Nests for CGRAs” by┬áJongeun Lee, Seongseok Seo, Hongsik Lee, and Hyeon Uk Sim, is accepted to this year’s CODES+ISSS (International Conference on Hardware-Software Codesign and System Synthesis).

CODES+ISSS is is a premier conference for embedded systems and hardware software co-design research, and held as part of ESWEEK (Embedded Systems Week) event, which also includes CASES (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems) and EMSOFT (International Conference on Embedded Software), along with a host of workshops and symposia. Congratulations again to those who did the hard work!

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