You are here:
Foswiki
>
Main Web
>
SimpleScalar
>
ResearchTopics
>
ReconfigurableComputingReadingList
(12 Feb 2014,
JongeunLee
)
Edit
Attach
Reconfigurable Computing Reading List
Recommended for beginners:
(Hartenstein 2001)
,
(Bougard 2008)
,
(Callahan 2000)
,
(Cardoso 2010)
Architectures often cited in the literature:
Garp
, MorphoSys,
ADRES
, RaPiD, PipeRench. An overview of those architectures can be found in
(Hartenstein 2001)
.
General RC Introduction
Compilation for RC
More about Architectures
Runtime Binary Translation approach
Background
On Compilation
On Low Power Design
General RC Introduction
(Kompton 2002)
Reconfigurable Computing: A Survey of Systems and Software, in ACM Computing Surveys
(Hartenstein 2001)
A decade of reconfigurable computing: A visionary retrospective, in DATE [Recommended, Short]
Overview and comparison of many often-cited architectures, by the creator of KressArray.
Compilation for RC
(Callahan 2000)
Adapting software pipelining for reconfigurable computing, in CASES [Garp]
(Mei 2003)
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling, in DATE [ADRES]
(Cardoso 2010)
Compiling for reconfigurable computing: A survey, in ACM Computing Surveys
Very long. Overview for both FPGA and CGRA compilation.
(Weinhardt 2001) Pipeline vectorization, in TCAD
(Park 2008) Edge-centric Modulo Scheduling for Coarse-Grained Reconfigurable Architectures, PACT.
(Clark 2008) VEAL: Virtualized Execution Accelerator for Loops, in ISCA
Dynamic translation approach.
More about Architectures
(Bougard 2008)
A Coarse-Grained Array Accelerator for Software Defined Radio Baseband Processing, in IEEE Micro [ADRES]
(Mei 2003)
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
Runtime Binary Translation approach
(Clark 2008)
VEAL: Virtualized execution accelerator for loops, in ISCA
(Beck 2005)
Exploiting Java through binary translation for low power embedded reconfigurable systems
(Beck 2008)
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
(Lysecky 2006)
Warp processors
(Bala 2000)
Dynamo: a transparent dynamic optimization system
(Stitt 2003)
Dynamic hardware software partitioning: a first approach, in DAC
(Stitt 2008)
Traversal Caches: A First Step towards FPGA Acceleration, in CODES+ISSS
These are some extra...
(Suganuma 2000)
Overview of the IBM Java Just-in-Time Compiler
(Suganuma 2001)
A dynamic optimization framework for a Java just-in-time compiler
(Arnold 2005)
A Survey of Adaptive Optimization in Virtual Machines
(Aycock 2003)
A brief history of just-in-time
Background
On Compilation
(Leupers 2010) A Short Introduction to Compilers (C Compilers for ASIPs), a book chapter
(Rau 1994) Iterative Modulo Scheduling: An algorithm for software pipelining loops, in MICRO
On Low Power Design
Power-efficient System Design
by Panda et al., 2010, Springer
E
dit
|
A
ttach
|
P
rint version
|
H
istory
: r22
<
r21
<
r20
<
r19
|
B
acklinks
|
V
iew wiki text
|
Edit
w
iki text
|
M
ore topic actions
Topic revision: r22 - 12 Feb 2014,
JongeunLee
Main
Log In
Main Web
Create New Topic
Index
Search
Changes
Notifications
RSS Feed
Statistics
Preferences
Webs
Main
Sandbox
System
Copyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Foswiki?
Send feedback