Logic Transistor Scaling And Roadmap

  • Speaker: Seok-Hee Lee
    • Department of electrical engineering, KAIST, Daejeon, Korea
    • Former manager at Intel
    • PhD in EE, Stanford University; MS & BS in EE, SNU.
  • Abstract: For the past four decades, relentless focus on transistor scaling and Moore’s Law led to ever-higher transistor performance and density, resulting in tremendous increases in functionality and performance. Historically, transistor scaling meant so-called "classic scaling" which was proposed by Dennard where gate oxide thickness (Tox), transistor length (Lg) and transistor width (W) were scaled by a constant factor (1/k) in order to provide a delay improvement of 1/k at constant power density. As the transistor gate length and the gate oxide thickness scale down, physical limitations, such as off-state leakage current and power density, make geometric scaling an increasingly challenging task. The introduction of strain silicon technology using embedded SiGe source/drain and high stress capping layers and high-k + metal gate transistors broke through some of these scaling barriers, continuing Moore’s Law. However, as dimensions are further reduced beyond 32nm node, there are a number of challenges to be overcome: capacitance, resistance, gate control, channel mobility, and variation. To continue historical trends of both area and performance improvement, novel solutions are required. This talk will review historical transistor scaling trends, traditional device scaling issues andrecent developments in the strain silicon and high-k + metal gate technology, including both gate-first and gate-last approaches, and then discuss potential future directions for continuing Moore’s Law into the next decade.
  • Time : 15:45-17:00 on March 31 (Thursday)
  • Location : Engineering Building 1, E204
  • Contact : Kibog Park, Ph.D.(2111), kibogpark@unist.ac.kr


  • History of integrated circuits:
    • 1st Getransistor (1947) -> 1958 Ge integrated circuit...
    • SRAM scaling trend: 0.5x/2years
    • classical MOSFET sclaing ENDED at the 90nm node in the early 2000s due to gate oxide scaling limits
  • Innovations to overcome "Traditional-scaling" limiters:
    • Mobility enhancement through uni-axial strained silicon technology innovation
    • Hi-K gate insulator to reduce gate leakage
    • Metal Gate to eliminate poly depletion
    • How strain Impacts Mobility?
  • PMOS mobility scaling
    • 90nm, 65nm, 45nm, 32nm
    • increasing Ge Concentration
    • Closer Proximity
    • RMG Strain Enhancement
  • Year 2003: Gate oxide ran out of stream

High-k + Metal Gate

High-k + Metal Gate Benefits:

  • High-k gate dielectric
    • Reduced gate leakage
    • Tox(e) scaling
  • Metal gates:
    • Eliminate polysilicon depletion
    • Resolves VT Pinning and poor mobility for high-k electrics

High-k + Metal Gate Challenges:

  • High-k gate dielectric
    • Poor mobility
    • Poor reliability
  • Metal gates
    • Dual band edge work functions
    • Thermal stability
    • Integration scheme

Replacement Metal Gate

  • Benefits
    • High Thermal budget available for Midsection
    • Low thermal budget for Metal Gate
    • Significant enhancement of strain
  • Scaling issue
    • Need to fill the narrow trench after the dummy polygate


  • Gate last approach (Intel)
  • Gate first approach (IBM)

Next step: EOT scaling or new architecture?

  • Multi-Gate Transistor Architecture
    • better SCE
    • Challenges in Multi-Gate FET
      • Implementing N & PMOS strain
      • High Parasitics
      • Very challenging fin patterning
      • High-k reliability
      • Process challenges with non-planar process
      • Very tight process control
  • Advanced Channel Materials: Ge

Summary: Beyond 22nm node

  • Low risk
    • Further enhancements in strain technology
    • Lg & Vcc scaling issues
  • Medium risk
    • Lg & Vcc scaling issues
  • High risk
    • Enables further Lg & Vcc scaling
  • Very high risk
    • Not ready

Intel's R&D for process technology development

  • PTD Portland Technology Development
    • Develops next gen CPU process technology
    • IDY Integration-Device-Yield
    • Advanced Design
      • SRAM design, Anlog design, Layout
    • Module
      • Lithography, Etch, Diffusion, Thin Film, Regen
    • Automation & operation
  • CR Component Research
    • Conducting research on the emerging technologies
    • Much smaller than PTD

How to be a successful engineer

  • Make sure you understand fundamentals
    • Most of problems you face are new
    • You have to go back to basics
  • Have a good communication skill
    • If you can't communicate, people cannot understand your point
  • Be a team player
    • Technology development is a concerted effort
  • Stay focused
    • It wants your sweat (or even blood)
Topic revision: r2 - 31 Mar 2011, ToanMai
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