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Compiler Papers in 2013 (Spring 2014)
Information
Meeting Times and Place
- When: Saturdays (or Fridays)
- Where: #504
- Discussion Record: \\altair\lab\Seminar\2014\
Schedule
| Day | Date | Presenter | Paper Title |
|---|---|---|---|
| 2 | 11/7 | Atul | Stochastic computing |
| 1 | 10/24 | Dong | Hyunh et al, PPoPP |
| ? | ?? | Hongsik | (cases 2013 20) From software to accelerators with LegUp high-level synthesis |
| 6 | 04/11 | Dong | (36.1) Reliable on-chip systems in the nano-era; Lessons learnt and future trends |
| 5 | 04/04 | Hongsik | (Yoon 2008 aspdac) SPKM: A Novel Graph Drawing based Algorithm for Application Mapping |
| ?? | (Park 2008 pact) Edge-centric Modulo Scheduling for Coarse-Grained Reconfigurable Architectures | ||
| 4 | 03/29 | Hyeonuk | (Mei 2002) DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures |
| 3 | 03/21 | Hongsik | REGIMap; Register-aware application mapping on Coarse-Grained Reconfigurable Architectures (CGRAs) |
| 2 | 03/14 | Dong | Aging-aware compiler-directed VLIW assignment for GPGPU architectures |
| 1 | 03/07 | Jongeun | Overview |
- Note: Schedule is subject to change.
- Note: Papers for Day 4 can be found here: \\altair\lab\Papers\Reconfigurable Computing\Mapping\
Reading List
DAC 2013
- (06.1) Defect tolerance in nanodevice-based programmable interconnects; Utilization beyond avoidance
- (06.2) An efficient and effective analytical placer for FPGAs
- (06.3) Throughput-oriented kernel porting onto FPGAs
- (06.4) Memory partitioning for multidimensional arrays in high-level synthesis
- (09.1) Aging-aware compiler-directed VLIW assignment for GPGPU architectures
- (09.2) Exploiting program-level masking and error propagation for constrained reliability optimization
- (09.3) REGIMap; Register-aware application mapping on Coarse-Grained Reconfigurable Architectures (CGRAs)
- (09.4) Polyhedral model based mapping optimization of loop nests for CGRAs
CASES 2013
- (cases 2013 05) Compiled multithreaded data paths on FPGAs for dynamic workloads
- (cases 2013 06) Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platforms
- (cases 2013 08) A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory
- (cases 2013 09) Exploiting phase inter-dependencies for faster iterative compiler optimization phase order searches
- (cases 2013 10) Platform-dependent code generation for embedded real-time software
- (cases 2013 11) CAeSaR; Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
- (cases 2013 12) Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator
- (cases 2013 14) Minimizing code size via page selection optimization on partitioned memory architectures
- (cases 2013 16) Hardware acceleration for programs in SSA form
- (cases 2013 20) From software to accelerators with LegUp high-level synthesis
- (cases 2013 21) Effective code discovery for ARM-Thumb mixed ISA binaries in a static binary translator
CASES 2013 Extra
- (cases 2013 07) Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism
- (cases 2013 17) Power-performance modeling on asymmetric multi-cores
- (cases 2013 18) Bitcoin and the age of Bespoke Silicon
Previous Seminars
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Topic revision: r14 - 21 Oct 2015, JongeunLee
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