EEE326 Projects

• Install Vivado
  • Remember to add pinmap file

• Open top-level design and do synthesis, creating a bitstream file

• Upload the bitstream file to Pynq-Z2 via web browswer

• Run FFT on Pynq FPGA, analyze runtime between SW numpy vs. Pynq FPGA acceleration

• Draw a graph showing runtime vs. array size for (i) SW numpy and (ii) Pynq FPGA. You may plot both graphs in a single figure.
• Verify the functionality of FFT, by feeding a sign function as the input to FFT. Verify the output of FFT.

• Make sure you have installed Vivado HLS

1. Write a module in Vivado HLS
2. Write test software
3. Run C-simulation
4. Verify the result of C-simulation
5. Run C-synthesis
6. Understand the result of C-synthesis
7. Run Cosim
8. Export the design as an IP
9. Import the IP in the Vivado design environment
10. Generate a bitstream
11. Create an overlay, and make a driver in Python

1. A compressed zip file of the generated IP files, (b) a bitstream file, (b) a Python Jupyter Notebook file;
2. A report, which should include a top-level diagram and the results of C-simulation, C-synthesis, and Cosimulation.

• This week's lab is similar to the previous week's. The main difference is that we use vectors for input and output.

• Vivado HLS
• Vivado
• Pynq board

• The previous lab was reviewed.

• Do the SAXPY example. Use the following function prototype (You may hard-code SIZE)

  void saxpy_hw(float *x, float *y, float a);     // y[i] = y[i] + a * x[i]
  

• Explore various methods to improve latency, and explain your findings in the report
• Submit the report and other files as usual

• Improve the performance of vadd using DMA
• Learn to use the hls::stream<> class

1. https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/cpp_kernels/simple_vadd/src/krnl_vadd.cpp
2. https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/HLS-Stream-Library
3. https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI4-Stream-Interfaces
4. UG902 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug902-vivado-high-level-synthesis.pdf

1. Study the vadd example in Ref. 1 above (see also Ref. 2 for HLS stream library). Note: This code may not run on the Pynq board.
2. To make it run on Pynq, we will mainly define/use push_stream and pop_stream functions along with some minor modification of the code.
3. Refer to Ref. 3 above for an exmple of how to use the ap_axiu type, which is defined in "ap_axi_sdata.h".
4. The rest of the flow is the same as in the previous lab.

• Implement the following SAXPY kernel in hardware using DMA as we learned in the lab.

  void saxpy_hw(float *z, float *x, float *y, float a);     // z[i] = a * x[i] + y[i]
  

  1. Note the order of the parameters.
  2. Follow the advice given by Jaewoo, TA, about performing buffer allocation in the constructor of a Python class.
• Submit source code (including testbench and header files if any and Python/Jupyter files) as well as your implementation files (IP, bitstream).
• Submit also a report, which should include the top-level diagram and the results of C-simulation, C-synthesis, and Cosimulation.

• Write a basic matrix multiplication kernel and verify its functionality on a Pynq board using the Python layer
• The use of DMA as in the previous lab is required.
• Optimization of the kernel (such as loop unrolling and the use of buffers) is NOT required.

• Implement a matrix multiplication kernel in hardware using Vivado HLS

  void matmul_hw(float *C, float *A, float *B);    // C = A * B
  

  • The sizes of the matrices are fixed as follows (you may hard-code them): float C[128][128], A[128][256], B[256][128] → float C[64][64], A[64][128], B[128][64]
  • Note: the top-level function of HLS module should have a slightly different prototype
• Use DMA as in the previous lab. Use the DMA function provided: dma_template.h.
  • The use of different template parameters in ap_axiu<32,4,5,5> is to avoid compatibility issues.
  • Since we're using DMA, the interface of the top-level function is very similar to that of the previous lab, but internally you'll have to change how to handle the values you recieve via AXIS. Specifically, you won't be able to use hls::stream<> as in the previous lab, but should store them in a local memory due to the complex access pattern required in the compute loop.
• As usual, submit your source code as well as your implementation files; Submit also a report, which should include the top-level diagram and the results of C-simulation, C-synthesis, and Cosimulation.

Learn how to use a Python (PyTorch)-based neural network framework and how to customize it so (some) inference computation can be offloaded to hardware.

1. MNIST neural network inference using PyTorch. (mnist.py)
   • Training included
2. Consider how to use HW MatMul for the MNIST neural network inference.
3. Write Python-based MNIST inference code. (numpymnist.py) (numpy_layer.py)
4. Override Linear layer with a function that calls MatMul HW.
5. In order to use integer MatMul HW, we have to change the type of input operands to MatMul. Modify the Python code accordingly (recall the quantization method discussed in lecture).

• Port the MNIST inference code to the Pynq board, by offloading the second layer to the hardware. For this, you'll need to generate N-bit integer MatMul hardware. (ARM-Python is already included in Pynq.)
• Try to minimize the parameter "N", which is the precision of activation and weight tensors.
• As usual, submit your source code as well as your implementation files. Submit also a report as usual (see the next item for the contents of the report).
• In the next lab, each team will give a presentation on their work, which should include the Pynq board execution result, classification accuracy, total execution time, and the value of the parameter "N".

Integrating the Pynq board and the hardware accelerator running on it with the application software is an important milestone. Hence we'll have a presentation session in the first half of the lab. Please prepare to present your Lab 7 results; best if everyone presents.

(i) Learn to use array partition and array reshape via a simple matrix multiplication example. (ii) Support arbitrarily large matrices.

1. Observe the inefficiency in a simple matrix multiplication example
2. Apply array partition and observe the difference in synthesis results
3. Consider how to support matrix multiplications with arbitrarily large size matrices
4. Implement your idea and verify the results

• Final project (due: TBD)

Here's the installation procedure.

1. System requirements: Windows10 or Ubuntu 18.04 only. (WARNING: Ubuntu 18.04.05 may NOT work.) Note: Large HDD space required (installation file alone is >10GB).
2. Visit https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html and download the installation file
   • You must have a Xilinx account.
   • The version we'll use is Xilinx Vivado 2020.1 (other versions may NOT work for our examples).
   • Download either Xilinx Unified Installer 2020.1: Windows Self Extracting Web Installer or Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer.
3. Apply patch: https://support.xilinx.com/s/article/76960. Otherwise, it will cause problems with Vivado HLS.
4. Apply PYNQ-Z2 board file: pynq-z2.zip. Unzip the file at your_vivado_path/Vivado/2020.1/data/boards/board_files. After unzipping, you should have data/boards/board_files/pynq-z2/A.0

It takes literally hours to complete installation. So start installing Vivado today!

Post your questions on BlackBoard if you have any!