Authors | Jongeun Lee, Kiyoung Choi, Nikil Dutt |
Publication | IEEE Design & Test of Computers (0740-7475), 20(1):26-33 |
Year | January 2003 |
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Abstract: Coarse-grained reconfigurable architectures can enhance the performance of critical loops and computation-intensive functions. Such architectures need efficient compilation techniques to map algorithms onto customized architectural configurations. A new compilation approach uses a generic reconfigurable architecture to tackle the memory bottleneck that typically limits the performance of many applications.