Intelligent Computing & Codesign Lab

In this year’s DATE (Design, Automation & Test in Europe), which is the largest European conference in the EDA (Electronic Design Automation) field, we have contributed two interactive presentation (IP) papers, which are published in 4 pages each and will appear in the IEEE Xplore as well. Congrats to those participants!

Here is the paper information (follow the links for full text).

• Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs, by J Lee, Y Jeong, and S Seo.
• Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication, by K Han, K Choi, and J Lee.